Abstract

The increasing needs of high speed and high throughput computing systems have prompted the need to develop efficient arithmetic units, the most important being adders, which form the heart of digital signal processor, microprocessor as well as any other high performance digital systems. The Kogge-Stone Adder (KSA), one of many architectures for adders, has the two characteristics of being based upon extremely shallow logic depth and a parallel prefix structure, which make it suitable to high-speed binary addition with large-width operands. The paper provides an in-depth discussion of the KoggeStone Adder as a scalable design that can be used addressing needs of the modern digital system which requires high-speed arithmetic functions. The present research paper examines the architectural merits of the Kogge-Stone Adder compared to other prefix adders including Brent- Kung, Han-Carlson and Ladner-Fischer adders with respect to its ability to provide low computation delay and tolerance to high level of parallelism. The KSA is studied in terms of logic depth, fan-out and complexity of wiring at different sizes of operand with synthesis of its implementation to FPGA and ASIC technologies. The simulation outcome proves that the Kogge-Stone Adder performs better than the baseline i.e., better propagation delay and better throughput however at the expense of more area and routing resources. Moreover, this paper presents optimized design solutions with the goal of trading off the conflicting goals of speed, area, power to make the KSA to be more of useful in application-specific integrated circuits (ASICs) and field- programmable gate array (FPGAs) in high-performance computing, embedded systems, and AI accelerators. Experimental tests prove the correctness of such optimizations to improving the efficiency and scalability of the adder implementation. Finally, it can be concluded that the Kogge-Stone Adder is an effective and scalable arithmetic, which delivers a strict set of performance requirements of the next generation of digital systems. It comes down to its ability to achieve high-throughput and low-latency computation which makes it a preferred option in terms of critical applications where the speed is of essence.

Authors

M. Sakthimohan, G. Elizabeth Rani
KIT - Kalaignarkarunanidhi Institute of Technology, India

Keywords

Kogge-Stone Adder (KSA), High-Speed Arithmetic Units, Parallel Prefix Adder, Low Latency Computation, High-Throughput Computing, Scalable Adder Architecture, Digital Signal Processing (DSP), High-Performance Computing (HPC), FPGA Implementation, ASIC Design