Abstract

The growing demand for high-speed, low-latency communication in next-generation wireless systems has driven the convergence of 4G LTE and 5G technologies. However, integrating 5G physical channels with existing LTE infrastructures presents a significant challenge due to inherent latency and bandwidth limitations in conventional baseband processing architectures. This study addresses these limitations by developing a Field-Programmable Gate Array (FPGA)-based LTE-M (LTE for Machines) acceleration framework that optimizes latency and enhances signal processing efficiency in hybrid 4G–5G networks. The proposed architecture leverages parallelized hardware design and reconfigurable logic to execute key baseband functions including modulation, demodulation, and channel coding at significantly higher throughput compared to traditional DSP or CPU-based systems. The design incorporates adaptive pipelining and low-complexity scheduling techniques to minimize processing delays in the physical layer, ensuring seamless support for Machine-Type Communication (MTC) and IoT-based applications over LTE-M channels. Experimental validation of the FPGA-based LTE-M framework showed a 37% reduction in end-to-end latency and a 42% improvement in throughput, with BER decreasing by 50% compared to conventional methods. In addition, FPGA resource utilization was optimized by 10–15%, and power consumption decreased by 30%, which shows both high performance and energy efficiency for hybrid 4G–5G network combination.

Authors

Varghese S Chooralil¹, John Chembukkavu², S. Brilly Sangeetha³
Rajagiri School of Engineering and Technology, India¹, IES College of Engineering, India^2,3

Keywords

FPGA Acceleration, LTE-M, 5G Physical Channel, Latency Reduction, Hybrid 4G–5G Combination