Abstract

Random number generation is very useful and highly applicable in cryptographic applications, and also true randomness is highly advantage for secure and data protection. Actual pseudo random generators not having enough entropy and may get predictability. Quantum Random Number Generators (QRNGs), based on quantum phenomena like single photon detection and provides enhanced unpredictability and security. In this work, we present the design and hardware realization of a SPAD (Single Photon Avalanche Diode) based Quantum Random Number Generator using a complete RTL to GDS flow. A behavioural Verilog model of SPAD operation was designed, and launching photon pulse detection, dead time effects and dead time effects. The design was simulated using several EDA tools are used to validate functionality. Thereafter, the RTL was Synthesized, Placed, Routed and verified to generate a GDSII layout. The proposed implementation illustrates a implementable strategy for integrating quantum enhanced randomness into secure hardware systems. The RTL to GDSII affirmation of compatibility for Application Specific Integration Circuit (ASIC) fabrication, enabling cryptographic applications such as Quantum Key Distribution (QKD) and hardware security module for low power circuits. By using Non-linear feedback shift Register (NLFSR) to strengthen randomness extraction and output Bit rates. Resilient randomness statistics verified by NIST test, and a total power consumption of only 0.272 m Watts noticeably less than legacy CMOS random number generators. So our work presents a scalable architecture for next-generation quantum entropy generators in secure communication systems, and also achieved better timing performance, power consumption, and randomness characteristics.

Authors

Vinod Babu Pusuluri, Shyam Perika, Bhanu Sri Venkata Vamsi Pandiri, Yamini Menda
Rajiv Gandhi University of Knowledge Technologies, India

Keywords

SPAD (Single Photon Avalanche Diode), QRNG (Quantum Random Number Generator), ASIC Fabrication, NLFSR (Non-Linear Feedback Shift Register)