Abstract

Approximate multipliers are often utilized in cases where small computation errors are tolerated in return for improved performance. This paper builds and evaluates an effective approximate multiplier that decreases power consumption, delays, and hardware complexity. The proposed design reduces the amount of logic used while maintaining a reasonable degree of correctness by changing some product production and accumulation phases. Performance is evaluated using parameters such as error metrics, power consumption, propagation delay and area usage. Experimental results show that, the BrentKung approximate multiplier gains up to 76% reduction in area, 57% reduction in power, and 62% reduction in delay, making it the most balanced design. The Ladner-Fischer design gives the highest improvement in power and PDP, with reductions of approximately 81%, while Kogge-Stone provides the highest area reduction of 80%. The designs are hence suitable for low-power VLSI systems and energy-efficient embedded applications.

Authors

Chintam Shravan, T. Srilatha, O. Anjali, V. Madhuri
Rajiv Gandhi University of Knowledge Technologies, India

Keywords

Approximate computing, Approximate multipliers, Parallel prefix adders (PPA), AxPPM, AxPO’s