Abstract

To mitigate the risks posed by scan-based side-channel attacks in integrated circuits, this work proposes a robust and adaptable architecture Dynamic Latch-Based Lock Architecture which builds on the foundational concepts of the parallel latch-based secure scan design. The proposed system is engineered to overcome limitations of earlier designs by introducing modular and parameterized key management components. Specifically, the design supports scalable key lengths of 8, 16, 32, and 64 bits, allowing customization based on the desired level of security and available hardware resources. In contrast to the fixed configurations in the base design, this architecture achieves area efficiency by minimizing the number of latches per scan path and strategically distributing logic through parameterizable modules. This reduction in latch overhead contributes to a more compact and optimized layout. In addition, clock gating mechanisms are integrated to dynamically disable portions of the scan logic during idle periods, thereby significantly reducing dynamic power consumption and improving overall energy efficiency. A notable feature of the design is a scalable Linear Feedback Shift Register (LFSR), whose length adapts to the chosen key size. This LFSR enhances security by performing runtime obfuscation of the circuit-under-test (CUT) output whenever a key mismatch is detected. This mechanism introduces unpredictability in scan outputs, effectively thwarting brute-force, SAT-based, and scan reconstruction attacks. To validate the practicality of the design, it was synthesized and tested on multiple standard ISCAS benchmark circuits including s27, s298, s1423, and s9234. Evaluation results show substantial improvements in both area and power efficiency, while preserving functional correctness and scan access for valid users. These outcomes demonstrate the scalability, effectiveness, and adaptability of the proposed architecture for modern secure hardware implementations.

Authors

M. Pavan, K.N. Madhusudhan
B.M.S. College of Engineering, India

Keywords

Secure Scan Design, Latch Based Architecture, Dynamic Obfuscation, Clock Gating, Design for Testability