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VLSI ARCHITECTURE FOR ERROR DETECTION AND CORRECTION BASED ON XOR AGAINST MULTIPLE CELL UPSETS WITH REDUCED REDUNDANT BITSV Bhanumathi, M Sunandini |
SIMULATION AND ANALYSIS OF A PASSIVE UPLINK-TRIGGERED LTE JAMMER USING PLL FREQUENCY CONTROLWilson Tchounna Tsabgou, Djuma Sumbiri |
A TWO LEVEL ARCHITECTURE USING CONSENSUS METHOD FOR GLOBAL DECISION MAKING AGAINST DDoS ATTACKSS.Seetha, P. Raviraj |